This invention relates to the phase synchronization of clock pulse signals.
To insure against the complete failure of a digital communication system in the event of the failure of the timing system, duplicated clock pulse signals are often independently generated as a clock maintenance strategy. In the event of a failure of one clock pulse source a standby clock can be switched onto the network to maintain network operation. Problems can arise, however, when during network operation the ability of the standby clock to be switched onto the network in place of the active clock is periodically tested. In particular, the standby clock pulse signal, although frequency locked to the active on-line clock signal, may lack phase synchronization with the active clock signal. When an out-of-phase standby clock is test-switched onto a digital network, an out-of-frame condition may result at the distant end of the digital system resulting in a loss of data. In order to prevent a possible out-of-frame condition each time the standby clock is test-switched onto the network, the standby and active clock signals should be phase synchronized within a predetermined tolerance.